The present invention relates to a method and/or architecture for complex programmable logic devices (CPLDs) generally and, more particularly, to a method and/or architecture for implementing internal registers using I/O cells of CPLDs.
Complex programmable logic devices (CPLDs) can have I/O cells that contain I/O registers and macrocells that contain macrocell registers. The I/O cells can be configured to provide either registered or combinatorial input/output signals to the I/O pins. When the I/O cells are configured to provide registered signals, a register in each I/O cell is configured to provide either a registered input or a registered output. When the I/O cells are configured as combinatorial inputs or outputs, the I/O registers are unused. An example of a CPLD having I/O cells may be found in co-pending applications U.S. Ser. No. 09/475,879, filed Dec. 30, 1999 and U.S. Ser. No. 09/539,943, filed Mar. 31, 2000, which are each hereby incorporated by reference in their entirety.
Frequently, not all available I/O pins of a device are used. The registers in both the I/O cells configured as combinatorial and the I/O cells of unused pins are effectively wasted. In some configurations (where smaller I/O count packages are used) up to 70% of the I/O cells are unused and significant available register resources are wasted.
A conventional approach to implementing registers of a logic circuit implemented in a CPLD includes: (i) implementing an input (edge of a design) register in an I/O cell, (ii) implementing an output (edge of a design) register in an I/O cell, and (iii) implementing an internal register (inside of a design) in a macrocell.
The term xe2x80x9cinternal registerxe2x80x9d as used herein refers to a simple storage element that can be used in general designs and also for pipeline balancing. The internal register does not require an input from combinatorial logic. When a macrocell is used to implement an internal register, the combinatorial logic of the macrocell is not available to the rest of the design.
It would be desirable to have a method and/or architecture where an unused I/O register may be used to implement an internal register when the I/O cell is either unused or configured to provide a combinatorial input and/or output.
The present invention concerns an I/O cell of a programmable logic device comprising a register, a first multiplexer, a second multiplexer, and a third multiplexer. The first multiplexer may be configured to present one of a plurality of signals to a data input of the register in response to a control signal. The second multiplexer may be configured to select either an output signal from the register or an external input signal in response to the control signal. The third multiplexer may be configured to select one of a number of inputs for presentation as an output signal of the I/O cell in response to the control signal. The register may be configured as an internal register of the programmable logic device when the I/O cell is configured to receive a combinatorial input signal and/or present a combinatorial output signal.
The objects, features and advantages of the present invention include providing a method and/or architecture for input/output cells of CPLDs that may (i) provide a significant benefit in pipelined designs and designs using registers as storage elements, (ii) involve no changes to silicon or architecture, (iii) be implemented as a software upgrade to existing devices, and/or (iv) make up to 19% more registers available to a device for a low silicon cost.